The present invention relates to integrated circuits, and more specifically to integrated circuit memories.
With each new generation of semiconductor memory, the size and density of the memory array increases. For example, when moving from a 4 Mb technology to a 16 Mb design, the array area must be increased in order to accommodate the additional memory cells. Increasing the array size, however, adversely effects certain electrical parameters required for optimal circuit performance.
In particular, increasing the size of the memory array leads to a problem known as xe2x80x9cresistance droopxe2x80x9d. In the memory array, long interconnect wires are used to carry voltages across the memory array. When a voltage source is connected to a long interconnect wire, a voltage drop is created on the interconnect wire due to the resistance of the interconnect wire. More specifically, points on the interconnect wire which are located far from the voltage source have a lower voltage potential than those which are located near the voltage source. This voltage differential in the memory array can adversely effect circuit performance and circuit yield.
Accordingly, a need exists for an efficient way to fabricate integrated circuits having memory arrays with reduced xe2x80x9cresistance droop.xe2x80x9d
The present invention overcomes the problems of the prior art memory circuits by providing a tiled memory with distributed charge source supply. According to one embodiment of the present invention, a plurality of memory tiles are arranged to form a tiled memory array with a common input/output interface in an integrated circuit device. In accordance with the present invention, each of the memory tiles in the tiled memory array has charge source circuitry to provide the sufficient reference voltages for proper operation of the memory tile. Further, the reference voltage for each tile is connected by abutment to the reference voltages associated with neighboring tiles. In addition, each memory tile may include local error detection and correction circuitry. To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry.
In one aspect of the present invention, a method for designing a tiled memory, includes the steps of designing a memory tile, comprising the steps of arranging a plurality of said memory tiles to form a tile array, designing an interface for selectively coupling the memory tiles to external logic, and integrating said interface and said tile array to form said tiled memory. The step of designing the memory tile includes the steps of designing a memory cell, arranging a plurality of said memory cells in a cell array, determining the charge requirements of said cell array, designing a charge source to supply said charge requirements, and integrating said charge source and said cell array to form said memory tile.